Tesla has quietly—no, plainly—renamed its AI accelerators. The prefix "AI" is out, "SI" is in. Chipnews reported on November 7 that the company's latest hardware roadmap rebrands its chips around "Super Intelligence," so the fourth-generation inference processor, once HW4 and then AI4, is now SI4. Musk confirmed that SpaceX AI would be renamed SpaceX SI for the same reason.
The eye-catcher is Dojo's comeback. Musk cancelled the project in August 2025, and in August 2026 he said SpaceX and xAI would use Nvidia hardware exclusively in their ground and space data centers. Now the planned Dojo D3 is back on the slide, described as a chiplet-based design that combines 2.5D and 3D packaging with stacked HBM. That's a clean break from the SRAM-centric wafer-scale architecture of earlier generations. D3 will be optimized for "space, training and scaling," and some SKUs are likely radiation-hardened. Performance figures, process node and timeline? All still under wraps.
The inference roadmap comes with concrete multiples. The sixth-generation accelerator SI6 is claimed to deliver 80 times SI4's compute and 9 times its memory—impressive on paper, though it won't arrive until 2029 to 2030. SI5 sits closer on the horizon. TSMC builds it on 3nm and Samsung on 2nm, in a multi-chip-module design, targeting a 40-fold gain over SI4. Power draw runs from 250W to 800W depending on the application, and memory is six times that of SI4 at about 96 GB. For anyone keeping score at home, Nvidia's Rubin GPU is already shipping to customers with 50 NVFP4 PFLOPS of inference and 35 NVFP4 PFLOPS of training performance.
As for SI4 itself, Samsung manufactures it on a 7nm-class process in a conventional FCBGA package, and it serves as the current baseline for Tesla's Full Self-Driving technology. Tesla has never published its absolute compute figure. Musk has said HW4 is 3 to 8 times as powerful as HW3, and HW3 carried an official rating of 72 TOPS.
SI6 sits on the farthest mark of the roadmap—2029 to 2030.